Recently, applications of digital control in DC-DC converters have attracted much attention. Digital control features stable control parameters, programmability, less passive components and easy implementation of advanced control algorithms, among other advantages. According to most literature on digitally controlled DC-DC converters, the frequency response presented is above 1 kHz, and with advancement in the measurement technology, the frequency response can now be measured to an accuracy of 10 Hz. Accordingly, it has been found that digitally controlled DC-DC converters suffer from an insufficient DC gain which, through analysis, is ascertained to arise from round-off effect.
As shown in FIG. 1, a digitally controlled DC-DC converter 10 includes a power stage 12 to convert an input voltage Vin into an output voltage Vo according to a PWM signal S3, a voltage divider 20 to divide the output voltage Vo to generate a feedback voltage Vd, an analog-to-digital converter (ADC) 18 to convert the analog voltage Vd into a digital signal S1, a digital compensator 16 for compensation of the digital signal S1 to generate a digital feedback signal S2, and a digital pulse width modulator (DPWM) 14 to generate the PWM signal S3 according to the digital signal S2. Generally, almost all analog compensators used in DC-DC converters include an integrator to provide an infinite DC gain, which makes the output voltage of the DC-DC converters equal to a preset voltage and thereby achieves zero error. After digitization, the coefficients of the digital compensator 16 are rounded off, and therefore an error occurs during the integration process, making it impossible for the output voltage Vo of the DC-DC converter 10 to stabilize at the preset voltage. An ideal integrator has a pole located at 0 Hz, which location is nevertheless very easily changed by round-off effect. More particularly, a pole located at a lower frequency is more susceptible to round-off effect. In other words, the lower frequency the pole is located at, the more the pole will displace due to round-off effect, and consequently the smaller the DC gain will be.
FIG. 2 is a diagram showing the frequency response of the digitally controlled DC-DC converter 10, in which waveform 22 represents the loop gain obtained when each coefficient of the digital compensator 16 has nine decimal bits, waveform 24 represents the loop gain obtained when each coefficient of the digital compensator 16 has twelve decimal bits, waveform 26 represents the loop gain obtained when each coefficient of the digital compensator 16 has sixteen decimal bits, waveform 28 represents the phase obtained when each coefficient of the digital compensator 16 has nine decimal bits, waveform 30 represents the phase obtained when each coefficient of the digital compensator 16 has twelve decimal bits, and waveform 32 represents the phase obtained when each coefficient of the digital compensator 16 has sixteen decimal bits. As shown in FIG. 2, the more decimal bits the coefficient of the digital compensator 16 has, the higher the loop gain of the DC-DC converter 10 in low frequency range will be. Therefore, to mitigate the influence of round-off effect on the coefficients of the digital compensator 16, a digital compensator 16 having more bits is often used, which however increases costs as well as computational complexity.
Up to now, the design of digital controllers for DC-DC converters has been much discussed in related literature, and in view of the fact that the ADC 18 and the digital pulse width modulator 14 in the feedback circuit sometimes cause limit-cycle oscillations, discussion has also been made on the nonlinear ADC 18 and the digital pulse width modulator 14 in the feedback circuit, with a view of designing an infinite-cycle digital controller. However, methods for DC gain improvement of the digitally controlled DC-DC converter 10 are still unavailable in the academia and the industry. Hence, it is desired a method for effectively improving the DC gain of a digitally controlled DC-DC converter under conditions of no-limit-cycle and a finite bit number to reduce steady-state error thereof.